1. Field of the Invention
The invention generally relates to the field of integrated circuit analog storage devices and in particular to a method and apparatus for performing voltage program operations within analog storage cells thereof.
2. Description of Related Art
U.S. Pat. No. 4,890,259 discloses a nonvolatile, high-density integrated circuit analog circuit recording and playback system wherein an analog input signal is sampled a plurality of times and then, as additional samples are being taken and temporarily held, a prior set of samples of the analog signal are parallel loaded into a plurality of storage sites, or cells, each comprising nonvolatile floating gate memory cells, preferably EEPROM cells. In that system, writing of the groups of samples into the respective storage cells is performed by iteratively providing a write pulse followed by a read operation for the respective cells to compare the information stored in each cell with the information held by the respective track and hold circuit. During successive write/read operations, the write pulse is increased in amplitude, with the write pulses to any cell being stopped or decoupled from the cell, after the information read from the cell in a previous read operation approximately equals the value held in the respective track and hold circuit.
U.S. Pat. No. 4,989,179 describes the use of analog memory in order to store digital data as multi-level analog information. Also described is an organization of the array of analog memory.
U.S. Pat. No. 5,126,967 provides an improvement to the system of U.S. Pat. No. 4,890,259 wherein one or more referenced storage columns are included in the array at each side of the storage side array and are used to store a reference signal at the same time that the adjacent storage cell stores a signal sample. During playback, the stored referenced signals are read back and weighted relative to each other in accordance with the relative column position of the signal storage cell being simultaneously read, with the output signal being taken as the difference between the sample signal read back and the reference signal read back (as weighted relative to each other as per the position in the row of the signal cell).
U.S. Pat. No. 5,241,494 also provides an improvement to the system of U.S. Pat. No. 4,890,259. In the system of U.S. Pat. No. 5,241,494, a multi-level iterative write process is provided for achieving programming of the analog storage cells with high-resolution. In particular, a coarse cycle of increasing voltage pulses are applied to a cell being written to quickly set the voltage of the cell to near a target voltage. The coarse cycle is achieved by employing a voltage ramp having a fairly steeply increasing voltage. During a subsequent fine cycle of recording, the stored voltage is fine-tuned by applying iterative pulses based on a voltage ramp having a more gradual voltage increase.
In each of the foregoing, a read operation is performed on each EEPROM cell after each respective voltage pulse is applied to determine whether the resulting voltage of the EEPROM cell is close to or exceeds a target voltage. If the resulting voltage exceeds the target voltage, the cell is said to be over-programmed. In the systems described, over-program can be corrected only by completely clearing the over-programmed cell and repeating the entire iterative write process to that cell. To avoid the need to dear a cell and repeat the iterative storage operations, slight amounts of over-program or under-program of the voltage are tolerated, thus resulting in less resolution than could theoretically be achieved. It would be desirable to provide an improved method for programming the voltage of analog storage cells wherein a higher degree of resolution may be achieved.
This improved resolution is useful for storage of digital data as multi-level analog information.
A program method which could operate more quickly by requiring fewer high voltage write operations is desirable since a smaller more economic embodiment results with fewer column driver circuits for the same sample rate.
When high speed programming is the system objective, then the number of high voltage write operations must be minimized.